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$63#64K65Compiler Options - General


Figure 22 Compiler Options - General
Secure Device
Adds the necessary code in the JEDEC download file to automatically allow the device programmer to blow the security fuse when programming. Not all programmers support this option.
Deactivate Unused OR Terms
In IFL devices, the OR-gate output array is driven by each of the AND-gate product terms. Normally, unused OR-gate inputs are left connected to the product term array so that new terms may be added. However, with this option, the unused OR-gate inputs are removed (deactivated) from the product term array. The result is reduced propagation delay from input to output.
Simulate
Creates the absolute file and automatically runs the CSIM logic simulator. CSIM is run with the option to create a list file. If the JEDEC name = PLD name option is selected it will be passed to CSIM creating a JEDEC download file with test vectors.
One hot bit State Machine

This option will cause the compiler to generate state machine equations as “one-hot-bit”. This has some distinct advantages in register rich architectures such as Xilinx devices. The fanin is reduced making routing much easier and timing problems associated with variable length feedback paths from register to register are eliminated. To use this feature each state machine must be defined with a “one-hot-bit” pattern. All state machines in the design will be treated as one-hot if this option is selected.






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